The invention relates to a semiconductor device comprising a semiconductor body of silicon with a p-type surface region adjoining a surface and provided with an n-type channel field effect transistor with insulated gate and with n-type source and drain zones provided in the surface region and mutually separated by an interposed channel region also adjoining the surface, while the surface region is provided with a buried p-type doped zone which extends below the channel region at a small distance from the surface and which has a higher doping concentration than the channel region. Such a device is known from U.S. Pat. No. 5,166,765.
The mobility of the charge carriers in the channel, often indicated with the symbol .mu. and expressed in cm.sup.2 /V.s, is an important parameter in MOS transistors with channel dimensions in the deep sub-micron region (for example, 0.1 micron), inter alia in view of the capacity of the transistor to conduct current. The mobility is strongly dependent on the value of the electric field in the channel, at least on the component of the field transverse to the surface. In general, the mobility decreases with an increasing field strength. The doping concentration in the channel should accordingly be very low in order to obtain a high mobility, for example of the order of 10.sup.15 atoms per cm.sup.3 (intrinsic silicon). Such a low doping level, however, is not possible because punch-through to the source occurs at very low drain voltages already with this doping. In addition, low channel doping levels in combination with very small dimensions (for example, a channel surface area of 0.1 .mu.m.times.0.1.mu.m) may lead to major fluctuations in the threshold voltage, which may be particularly unfavorable at lower supply voltages owing to fluctuations in the doping level. These problems are solved in principle in a transistor as described in the cited U.S. Pat. No. 5,166,765. In this known transistor, the channel region comprises an intrinsic surface region which adjoins the surface, has a thickness of a few tens of nanometers, and is situated above and adjoining a thin p-type layer having a high concentration of boron atoms, for example of the order of 10.sup.18 per cm.sup.3. A transistor constructed in this way has a high mobility of charge carriers, a high punch-through voltage, and a good threshold voltage. The extremely small dimensions, however, render it difficult to manufacture such a transistor in a reliable and reproducible manner. Moreover, a separate implantation of As ions is required in the channel region of the transistor so as to compensate for the B atoms present and make the silicon in the channel region intrinsic. Such an As implantation in the channel, however, is disadvantageous for the mobility of the charge carriers and for the process control, for example as regards the threshold voltage V.sub.T.